`timescale 1ns / 1ps

module InSight #(
  parameter       SIMULATION = "FALSE",
  parameter       LANES = 4
)(
  input           SYS_CLKp,
  input           SYS_CLKn,
  input           SYS_RST,
  
  input           UART_RX,
  output          UART_TX,
  
  output  [0:0]   DDR3_CLKp,
  output  [0:0]   DDR3_CLKn,
  output  [0:0]   DDR3_CKE,
  output  [12:0]  DDR3_A,
  output  [2:0]   DDR3_BA,
  output          DDR3_CASn,
  output          DDR3_RASn,
  output          DDR3_WEn,
  output  [0:0]   DDR3_CSn,
  inout   [63:0]  DDR3_DQ,
  inout   [7:0]   DDR3_DQSp,
  inout   [7:0]   DDR3_DQSn,
  output  [7:0]   DDR3_DM,
  output  [0:0]   DDR3_ODT,
  output          DDR3_RSTn,
  
  input           ETHERNET_MII_TX_CLK,
  output  [7:0]   ETHERNET_TXD,
  output          ETHERNET_TX_EN,
  output          ETHERNET_TX_ER,
  output          ETHERNET_TX_CLK,
  input   [7:0]   ETHERNET_RXD,
  input           ETHERNET_RX_DV,
  input           ETHERNET_RX_ER,
  input           ETHERNET_RX_CLK,
  output          ETHERNET_MDC,
  inout           ETHERNET_MDIO,
  output          ETHERNET_RSTn,
  
  output  [23:0]  FLASH_A,
  inout   [15:0]  FLASH_DQ,
  output          FLASH_WEn,
  output          FLASH_OEn,
  output          FLASH_CEn,
  
  output  [7:0]   LED,
  input   [7:0]   DIP,
  output          LED_C,
  output          LED_W,
  output          LED_S,
  output          LED_E,
  output          LED_N,

  inout   [6:0]   LCD_GPIO,

  input           PCIE_PERSTn,
  
  input           PCIE_UP_REFCLKp,
  input           PCIE_UP_REFCLKn,
  input   [3:0]   PCIE_UP_RXp,
  input   [3:0]   PCIE_UP_RXn,
  output  [3:0]   PCIE_UP_TXp,
  output  [3:0]   PCIE_UP_TXn,

  input           PCIE_DN_REFCLKp,
  input           PCIE_DN_REFCLKn,
  input   [3:0]   PCIE_DN_RXp,
  input   [3:0]   PCIE_DN_RXn,
  output  [3:0]   PCIE_DN_TXp,
  output  [3:0]   PCIE_DN_TXn
  );


  wire sys_clk;
  wire pcie_up_clk;
  wire pcie_dn_clk;
  IBUFGDS IBUFGDS_sys_clk (.O(sys_clk), .I(SYS_CLKp), .IB(SYS_CLKn));
  IBUFDS_GTXE1 IBUFDS_GTXE1_pcie_up_clk (.O(pcie_up_clk), .I(PCIE_UP_REFCLKp), .IB(PCIE_UP_REFCLKn), .CEB(1'b0));
  IBUFDS_GTXE1 IBUFDS_GTXE1_pcie_dn_clk (.O(pcie_dn_clk), .I(PCIE_DN_REFCLKp), .IB(PCIE_DN_REFCLKn), .CEB(1'b0));

  wire clk;
  wire locked;
  wire ddr_init_done;
  wire linkup;
  
  wire  [31:0]  uc_s_awaddr;
  wire          uc_s_awvalid;
  wire          uc_s_awready;
  wire  [31:0]  uc_s_wdata;
  wire  [3:0]   uc_s_wstrb;
  wire          uc_s_wvalid;
  wire          uc_s_wready;
  wire  [1:0]   uc_s_bresp;
  wire          uc_s_bvalid;
  wire          uc_s_bready;
  wire  [31:0]  uc_s_araddr;
  wire          uc_s_arvalid;
  wire          uc_s_arready;
  wire  [31:0]  uc_s_rdata;
  wire  [1:0]   uc_s_rresp;
  wire          uc_s_rvalid;
  wire          uc_s_rready;

  wire  [31:0]  pab_s_awaddr;
  wire          pab_s_awvalid;
  wire          pab_s_awready;
  wire  [31:0]  pab_s_wdata;
  wire  [3:0]   pab_s_wstrb;
  wire          pab_s_wvalid;
  wire          pab_s_wready;
  wire  [1:0]   pab_s_bresp;
  wire          pab_s_bvalid;
  wire          pab_s_bready;
  wire  [31:0]  pab_s_araddr;
  wire          pab_s_arvalid;
  wire          pab_s_arready;
  wire  [31:0]  pab_s_rdata;
  wire  [1:0]   pab_s_rresp;
  wire          pab_s_rvalid;
  wire          pab_s_rready;

  wire  [31:0]  an_s_awaddr;
  wire          an_s_awvalid;
  wire          an_s_awready;
  wire  [31:0]  an_s_wdata;
  wire  [3:0]   an_s_wstrb;
  wire          an_s_wvalid;
  wire          an_s_wready;
  wire  [1:0]   an_s_bresp;
  wire          an_s_bvalid;
  wire          an_s_bready;
  wire  [31:0]  an_s_araddr;
  wire          an_s_arvalid;
  wire          an_s_arready;
  wire  [31:0]  an_s_rdata;
  wire  [1:0]   an_s_rresp;
  wire          an_s_rvalid;
  wire          an_s_rready;

  wire  [31:0]  ex_s_awaddr;
  wire          ex_s_awvalid;
  wire          ex_s_awready;
  wire  [31:0]  ex_s_wdata;
  wire  [3:0]   ex_s_wstrb;
  wire          ex_s_wvalid;
  wire          ex_s_wready;
  wire  [1:0]   ex_s_bresp;
  wire          ex_s_bvalid;
  wire          ex_s_bready;
  wire  [31:0]  ex_s_araddr;
  wire          ex_s_arvalid;
  wire          ex_s_arready;
  wire  [31:0]  ex_s_rdata;
  wire  [1:0]   ex_s_rresp;
  wire          ex_s_rvalid;
  wire          ex_s_rready;
  
  wire  [31:0]  pab_s0_awaddr;
  wire          pab_s0_awvalid;
  wire          pab_s0_awready;
  wire  [127:0] pab_s0_wdata;
  wire  [15:0]  pab_s0_wstrb;
  wire          pab_s0_wvalid;
  wire          pab_s0_wready;
  wire  [1:0]   pab_s0_bresp;
  wire          pab_s0_bvalid;
  wire          pab_s0_bready;
  wire  [31:0]  pab_s0_araddr;
  wire          pab_s0_arvalid;
  wire          pab_s0_arready;
  wire  [127:0] pab_s0_rdata;
  wire  [1:0]   pab_s0_rresp;
  wire          pab_s0_rvalid;
  wire          pab_s0_rready;

  wire  [31:0]  pab_m0_awaddr;
  wire  [7:0]   pab_m0_awlen;
  wire          pab_m0_awvalid;
  wire          pab_m0_awready;
  wire  [127:0] pab_m0_wdata;
  wire  [15:0]  pab_m0_wstrb;
  wire          pab_m0_wlast;
  wire          pab_m0_wvalid;
  wire          pab_m0_wready;
  wire  [1:0]   pab_m0_bresp;
  wire          pab_m0_bvalid;
  wire          pab_m0_bready;
  wire  [31:0]  pab_m0_araddr;
  wire  [7:0]   pab_m0_arlen;
  wire          pab_m0_arvalid;
  wire          pab_m0_arready;
  wire  [127:0] pab_m0_rdata;
  wire          pab_m0_rlast;
  wire  [1:0]   pab_m0_rresp;
  wire          pab_m0_rvalid;
  wire          pab_m0_rready;

  wire  [31:0]  an_up_awaddr;
  wire  [7:0]   an_up_awlen;
  wire  [2:0]   an_up_awsize;
  wire  [1:0]   an_up_awburst;
  wire          an_up_awvalid;
  wire          an_up_awready;
  wire  [127:0] an_up_wdata;
  wire  [15:0]  an_up_wstrb;
  wire          an_up_wlast;
  wire          an_up_wvalid;
  wire          an_up_wready;
  wire  [1:0]   an_up_bresp;
  wire          an_up_bvalid;
  wire          an_up_bready;
  
  wire  [31:0]  an_dn_awaddr;
  wire  [7:0]   an_dn_awlen;
  wire  [2:0]   an_dn_awsize;
  wire  [1:0]   an_dn_awburst;
  wire          an_dn_awvalid;
  wire          an_dn_awready;
  wire  [127:0] an_dn_wdata;
  wire  [15:0]  an_dn_wstrb;
  wire          an_dn_wlast;
  wire          an_dn_wvalid;
  wire          an_dn_wready;
  wire  [1:0]   an_dn_bresp;
  wire          an_dn_bvalid;
  wire          an_dn_bready;
  
  wire  [0:0]   ex_m_arid;
  wire  [31:0]  ex_m_araddr;
  wire  [7:0]   ex_m_arlen;
  wire  [2:0]   ex_m_arsize;
  wire  [1:0]   ex_m_arburst;
  wire          ex_m_arvalid;
  wire          ex_m_arready;
  wire  [0:0]   ex_m_rid;
  wire  [127:0] ex_m_rdata;
  wire  [1:0]   ex_m_rresp;
  wire          ex_m_rlast;
  wire          ex_m_rvalid;
  wire          ex_m_rready;
  wire  [0:0]   ex_m_awid;
  wire  [31:0]  ex_m_awaddr;
  wire  [7:0]   ex_m_awlen;
  wire  [2:0]   ex_m_awsize;
  wire  [1:0]   ex_m_awburst;
  wire          ex_m_awvalid;
  wire          ex_m_awready;
  wire  [127:0] ex_m_wdata;
  wire  [15:0]  ex_m_wstrb;
  wire          ex_m_wlast;
  wire          ex_m_wvalid;
  wire          ex_m_wready;
  wire  [0:0]   ex_m_bid;
  wire  [1:0]   ex_m_bresp;
  wire          ex_m_bvalid;
  wire          ex_m_bready;
/*
  wire          id0_s_tvalid;
  wire          id0_s_tready;
  wire [127:0]  id0_s_tdata;
  wire [3:0]    id0_s_tstrb;
  wire          id0_s_tlast;
  wire          id0_m_tvalid;
  wire          id0_m_tready;
  wire [127:0]  id0_m_tdata;
  wire [3:0]    id0_m_tstrb;
  wire          id0_m_tlast;

  wire          id1_s_tvalid;
  wire          id1_s_tready;
  wire [127:0]  id1_s_tdata;
  wire [3:0]    id1_s_tstrb;
  wire          id1_s_tlast;
  wire          id1_m_tvalid;
  wire          id1_m_tready;
  wire [127:0]  id1_m_tdata;
  wire [3:0]    id1_m_tstrb;
  wire          id1_m_tlast;
*/
  wire          an_up_tvalid;
  wire [127:0]  an_up_tdata;
  wire [3:0]    an_up_tstrb;
  wire          an_up_tlast;
  wire          an_dn_tvalid;
  wire [127:0]  an_dn_tdata;
  wire [3:0]    an_dn_tstrb;
  wire          an_dn_tlast;
  
  wire          pd_s_tvalid;
  wire          pd_s_tready;
  wire [127:0]  pd_s_tdata;
  wire [3:0]    pd_s_tstrb;
  wire          pd_s_tlast;
  wire          pd_m_tvalid;
  wire          pd_m_tready;
  wire [127:0]  pd_m_tdata;
  wire [3:0]    pd_m_tstrb;
  wire          pd_m_tlast;

  wire          ed_s_tvalid;
  wire          ed_s_tready;
  wire [127:0]  ed_s_tdata;
  wire [3:0]    ed_s_tstrb;
  wire          ed_s_tlast;
  wire          ed_m_tvalid;
  wire          ed_m_tready;
  wire [127:0]  ed_m_tdata;
  wire [3:0]    ed_m_tstrb;
  wire          ed_m_tlast;
  
  wire SelPabEx = 1'b0; /*0: PAB; 1: EX*/
/*
  assign uc_s_tvalid  = SelPabEx ? ex_m_tvalid : pab_m_tvalid; 
  assign uc_s_tdata   = SelPabEx ? ex_m_tdata  : pab_m_tdata; 
  assign uc_s_tstrb   = SelPabEx ? ex_m_tstrb  : pab_m_tstrb; 
  assign uc_s_tlast   = SelPabEx ? ex_m_tlast  : pab_m_tlast; 
  assign uc_m_tready  = SelPabEx ? ex_s_tready : pab_s_tready;

  assign pab_s_tvalid = SelPabEx ? 1'b0 : uc_m_tvalid;
  assign pab_s_tdata = SelPabEx ? 128'b0 : uc_m_tdata;
  assign pab_s_tstrb = SelPabEx ? 4'b0 : uc_m_tstrb;
  assign pab_s_tlast = SelPabEx ? 1'b0 : uc_m_tlast;
  assign pab_m_tready = SelPabEx ? 1'b0 : uc_s_tready;

  assign an_up_tvalid = uc_s_tvalid && uc_s_tready;
  assign an_up_tdata = uc_s_tdata;
  assign an_up_tstrb = uc_s_tstrb;
  assign an_up_tlast = uc_s_tlast;
  assign an_dn_tvalid = uc_m_tvalid && uc_m_tready;
  assign an_dn_tdata = uc_m_tdata;
  assign an_dn_tstrb = uc_m_tstrb;
  assign an_dn_tlast = uc_m_tlast;
  
  assign ex_s_tvalid = SelPabEx ? uc_m_tvalid : 1'b0;
  assign ex_s_tdata = SelPabEx ? uc_m_tdata : 127'b0;
  assign ex_s_tstrb = SelPabEx ? uc_m_tstrb : 4'b0;
  assign ex_s_tlast = SelPabEx ? uc_m_tlast : 1'b0;
  assign ex_m_tready = SelPabEx ? uc_s_tready : 1'b0;
*/

  Switch #(
    .SIMULATION     (SIMULATION),
    .LANES          (LANES))
  sw(
    .CLK(clk),
    .RST(!locked),
    
    .PCIE_PERSTn      (PCIE_PERSTn),
  
    .PCIE_UP_REFCLK   (pcie_up_clk),
    .PCIE_UP_TXn      (PCIE_UP_TXn),
    .PCIE_UP_TXp      (PCIE_UP_TXp),
    .PCIE_UP_RXn      (PCIE_UP_RXn),
    .PCIE_UP_RXp      (PCIE_UP_RXp),
    .PCIE_UP_LINKUP   (linkup),
    
    .PCIE_DN0_REFCLK   (),
    .PCIE_DN0_TXn      (),
    .PCIE_DN0_TXp      (),
    .PCIE_DN0_RXn      (),
    .PCIE_DN0_RXp      (),
    .PCIE_DN0_LINKUP   (),

    .PCIE_DN1_REFCLK   (),
    .PCIE_DN1_TXn      (),
    .PCIE_DN1_TXp      (),
    .PCIE_DN1_RXn      (),
    .PCIE_DN1_RXp      (),
    .PCIE_DN1_LINKUP   (),

    .S_DN0_TVALID     (pd_m_tvalid),
    .S_DN0_TREADY     (pd_m_tready),
    .S_DN0_TDATA      (pd_m_tdata ),
    .S_DN0_TSTRB      (pd_m_tstrb ),
    .S_DN0_TLAST      (pd_m_tlast ),
    .M_DN0_TVALID     (pd_s_tvalid),
    .M_DN0_TREADY     (pd_s_tready),
    .M_DN0_TDATA      (pd_s_tdata ),
    .M_DN0_TSTRB      (pd_s_tstrb ),
    .M_DN0_TLAST      (pd_s_tlast ),
    
    .S_DN1_TVALID     (ed_m_tvalid),
    .S_DN1_TREADY     (ed_m_tready),
    .S_DN1_TDATA      (ed_m_tdata ),
    .S_DN1_TSTRB      (ed_m_tstrb ),
    .S_DN1_TLAST      (ed_m_tlast ),
    .M_DN1_TVALID     (ed_s_tvalid),
    .M_DN1_TREADY     (ed_s_tready),
    .M_DN1_TDATA      (ed_s_tdata ),
    .M_DN1_TSTRB      (ed_s_tstrb ),
    .M_DN1_TLAST      (ed_s_tlast )
  );

  PcieAxiBridgeDevice
  pabd(
    .CLK            (clk      ),
    .RST            (!locked     ),

    .S_TVALID       (pd_s_tvalid ),
    .S_TREADY       (pd_s_tready ),
    .S_TDATA        (pd_s_tdata  ),
    .S_TSTRB        (pd_s_tstrb  ),
    .S_TLAST        (pd_s_tlast  ),
    .M_TVALID       (pd_m_tvalid ),
    .M_TREADY       (pd_m_tready ),
    .M_TDATA        (pd_m_tdata  ),
    .M_TSTRB        (pd_m_tstrb  ),
    .M_TLAST        (pd_m_tlast  ),

    .S_AWADDR     (pab_s_awaddr ),
    .S_AWVALID    (pab_s_awvalid),
    .S_AWREADY    (pab_s_awready),
    .S_WDATA      (pab_s_wdata  ),
    .S_WSTRB      (pab_s_wstrb  ),
    .S_WVALID     (pab_s_wvalid ),
    .S_WREADY     (pab_s_wready ),
    .S_BRESP      (pab_s_bresp  ),
    .S_BVALID     (pab_s_bvalid ),
    .S_BREADY     (pab_s_bready ),
    .S_ARADDR     (pab_s_araddr ),
    .S_ARVALID    (pab_s_arvalid),
    .S_ARREADY    (pab_s_arready),
    .S_RDATA      (pab_s_rdata  ),
    .S_RRESP      (pab_s_rresp  ),
    .S_RVALID     (pab_s_rvalid ),
    .S_RREADY     (pab_s_rready ),

    .S0_AWADDR       (pab_s0_awaddr ),
    .S0_AWVALID      (pab_s0_awvalid),
    .S0_AWREADY      (pab_s0_awready),
    .S0_WDATA        (pab_s0_wdata  ),
    .S0_WSTRB        (pab_s0_wstrb  ),
    .S0_WVALID       (pab_s0_wvalid ),
    .S0_WREADY       (pab_s0_wready ),
    .S0_BRESP        (pab_s0_bresp  ),
    .S0_BVALID       (pab_s0_bvalid ),
    .S0_BREADY       (pab_s0_bready ),
    .S0_ARADDR       (pab_s0_araddr ),
    .S0_ARVALID      (pab_s0_arvalid),
    .S0_ARREADY      (pab_s0_arready),
    .S0_RDATA        (pab_s0_rdata  ),
    .S0_RRESP        (pab_s0_rresp  ),
    .S0_RVALID       (pab_s0_rvalid ),
    .S0_RREADY       (pab_s0_rready ),
  
    .M0_AWADDR       (pab_m0_awaddr ),
    .M0_AWLEN        (pab_m0_awlen  ),
    .M0_AWVALID      (pab_m0_awvalid),
    .M0_AWREADY      (pab_m0_awready),
    .M0_WDATA        (pab_m0_wdata  ),
    .M0_WSTRB        (pab_m0_wstrb  ),
    .M0_WLAST        (pab_m0_wlast  ),
    .M0_WVALID       (pab_m0_wvalid ),
    .M0_WREADY       (pab_m0_wready ),
    .M0_BRESP        (pab_m0_bresp  ),
    .M0_BVALID       (pab_m0_bvalid ),
    .M0_BREADY       (pab_m0_bready ),
    .M0_ARADDR       (pab_m0_araddr ),
    .M0_ARLEN        (pab_m0_arlen  ),
    .M0_ARVALID      (pab_m0_arvalid),
    .M0_ARREADY      (pab_m0_arready),
    .M0_RDATA        (pab_m0_rdata  ),
    .M0_RRESP        (pab_m0_rresp  ),
    .M0_RLAST        (pab_m0_rlast  ),
    .M0_RVALID       (pab_m0_rvalid ),
    .M0_RREADY       (pab_m0_rready )
  );

  ExerciserDevice 
  ed(
    .CLK            (clk      ),
    .RST            (!locked     ),

    .S_AWADDR       (ex_s_awaddr),
    .S_AWVALID      (ex_s_awvalid),
    .S_AWREADY      (ex_s_awready),
    .S_WDATA        (ex_s_wdata),
    .S_WSTRB        (ex_s_wstrb),
    .S_WVALID       (ex_s_wvalid),
    .S_WREADY       (ex_s_wready),
    .S_BRESP        (ex_s_bresp),
    .S_BVALID       (ex_s_bvalid),
    .S_BREADY       (ex_s_bready),
    .S_ARADDR       (ex_s_araddr),
    .S_ARVALID      (ex_s_arvalid),
    .S_ARREADY      (ex_s_arready),
    .S_RDATA        (ex_s_rdata),
    .S_RRESP        (ex_s_rresp),
    .S_RVALID       (ex_s_rvalid),
    .S_RREADY       (ex_s_rready),

    .S_TVALID       (ed_s_tvalid),
    .S_TREADY       (ed_s_tready),
    .S_TDATA        (ed_s_tdata),
    .S_TSTRB        (ed_s_tstrb),
    .S_TLAST        (ed_s_tlast),
    .M_TVALID       (ed_m_tvalid),
    .M_TREADY       (ed_m_tready),
    .M_TDATA        (ed_m_tdata),
    .M_TSTRB        (ed_m_tstrb),
    .M_TLAST        (ed_m_tlast),

    .M_ARID         (ex_m_arid      ),
    .M_ARADDR       (ex_m_araddr    ),
    .M_ARLEN        (ex_m_arlen     ),
    .M_ARSIZE       (ex_m_arsize    ),
    .M_ARBURST      (ex_m_arburst   ),
    .M_ARVALID      (ex_m_arvalid   ),
    .M_ARREADY      (ex_m_arready   ),
    .M_RID          (ex_m_rid       ),
    .M_RDATA        (ex_m_rdata     ),
    .M_RRESP        (ex_m_rresp     ),
    .M_RLAST        (ex_m_rlast     ),
    .M_RVALID       (ex_m_rvalid    ),
    .M_RREADY       (ex_m_rready    ),
    .M_AWID         (ex_m_awid      ),
    .M_AWADDR       (ex_m_awaddr    ),
    .M_AWLEN        (ex_m_awlen     ),
    .M_AWSIZE       (ex_m_awsize    ),
    .M_AWBURST      (ex_m_awburst   ),
    .M_AWVALID      (ex_m_awvalid   ),
    .M_AWREADY      (ex_m_awready   ),
    .M_WDATA        (ex_m_wdata     ),
    .M_WSTRB        (ex_m_wstrb     ),
    .M_WLAST        (ex_m_wlast     ),
    .M_WVALID       (ex_m_wvalid    ),
    .M_WREADY       (ex_m_wready    ),
    .M_BID          (ex_m_bid       ),
    .M_BRESP        (ex_m_bresp     ),
    .M_BVALID       (ex_m_bvalid    ),
    .M_BREADY       (ex_m_bready    )
  );
  
  capture_module an(
    .CLK            (clk      ),
    .RST            (!locked     ),
  
    .S_AWADDR       (an_s_awaddr),
    .S_AWVALID      (an_s_awvalid),
    .S_AWREADY      (an_s_awready),
    .S_WDATA        (an_s_wdata),
    .S_WSTRB        (an_s_wstrb),
    .S_WVALID       (an_s_wvalid),
    .S_WREADY       (an_s_wready),
    .S_BRESP        (an_s_bresp),
    .S_BVALID       (an_s_bvalid),
    .S_BREADY       (an_s_bready),
    .S_ARADDR       (an_s_araddr),
    .S_ARVALID      (an_s_arvalid),
    .S_ARREADY      (an_s_arready),
    .S_RDATA        (an_s_rdata),
    .S_RRESP        (an_s_rresp),
    .S_RVALID       (an_s_rvalid),
    .S_RREADY       (an_s_rready),

    .S_UP_TVALID    (an_up_tvalid),
    .S_UP_TDATA     (an_up_tdata),
    .S_UP_TSTRB     (an_up_tstrb),
    .S_UP_TLAST     (an_up_tlast),
    .S_DN_TVALID    (an_dn_tvalid),
    .S_DN_TDATA     (an_dn_tdata),
    .S_DN_TSTRB     (an_dn_tstrb),
    .S_DN_TLAST     (an_dn_tlast),

    .M_UP_AWADDR    (an_up_awaddr),
    .M_UP_AWLEN     (an_up_awlen),
    .M_UP_AWSIZE    (an_up_awsize),
    .M_UP_AWBURST   (an_up_awburst),
    .M_UP_AWVALID   (an_up_awvalid),
    .M_UP_AWREADY   (an_up_awready),
    .M_UP_WDATA     (an_up_wdata),
    .M_UP_WSTRB     (an_up_wstrb),
    .M_UP_WLAST     (an_up_wlast),
    .M_UP_WVALID    (an_up_wvalid),
    .M_UP_WREADY    (an_up_wready),
    .M_UP_BRESP     (an_up_bresp),
    .M_UP_BVALID    (an_up_bvalid),
    .M_UP_BREADY    (an_up_bready),

    .M_DN_AWADDR    (an_dn_awaddr),
    .M_DN_AWLEN     (an_dn_awlen),
    .M_DN_AWSIZE    (an_dn_awsize),
    .M_DN_AWBURST   (an_dn_awburst),
    .M_DN_AWVALID   (an_dn_awvalid),
    .M_DN_AWREADY   (an_dn_awready),
    .M_DN_WDATA     (an_dn_wdata),
    .M_DN_WSTRB     (an_dn_wstrb),
    .M_DN_WLAST     (an_dn_wlast),
    .M_DN_WVALID    (an_dn_wvalid),
    .M_DN_WREADY    (an_dn_wready),
    .M_DN_BRESP     (an_dn_bresp),
    .M_DN_BVALID    (an_dn_bvalid),
    .M_DN_BREADY    (an_dn_bready)
  );
  
  eps eps(
    .SYS_CLK          (sys_clk),
    .SYS_RST          (SYS_RST),
`ifndef SIM    
    .UART_RX          (UART_RX),
    .UART_TX          (UART_TX),
    
    .DDR_CLKp         (DDR3_CLKp),
    .DDR_CLKn         (DDR3_CLKn),
    .DDR_CKE          (DDR3_CKE),
    .DDR_A            (DDR3_A),
    .DDR_BA           (DDR3_BA),
    .DDR_CASn         (DDR3_CASn),
    .DDR_RASn         (DDR3_RASn),
    .DDR_WEn          (DDR3_WEn),
    .DDR_CSn          (DDR3_CSn),
    .DDR_DQ           (DDR3_DQ),
    .DDR_DQSp         (DDR3_DQSp),
    .DDR_DQSn         (DDR3_DQSn),
    .DDR_DM           (DDR3_DM),
    .DDR_ODT          (DDR3_ODT),
    .DDR_RSTn         (DDR3_RSTn),
    
    .ETHERNET_MII_TX_CLK(ETHERNET_MII_TX_CLK),
    .ETHERNET_TXD     (ETHERNET_TXD),
    .ETHERNET_TX_EN   (ETHERNET_TX_EN),
    .ETHERNET_TX_ER   (ETHERNET_TX_ER),
    .ETHERNET_TX_CLK  (ETHERNET_TX_CLK),
    .ETHERNET_RXD     (ETHERNET_RXD),
    .ETHERNET_RX_DV   (ETHERNET_RX_DV),
    .ETHERNET_RX_ER   (ETHERNET_RX_ER),
    .ETHERNET_RX_CLK  (ETHERNET_RX_CLK),
    .ETHERNET_MDC     (ETHERNET_MDC),
    .ETHERNET_MDIO    (ETHERNET_MDIO),
    .ETHERNET_RSTn    (ETHERNET_RSTn),
    
    .FLASH_A          (FLASH_A),
    .FLASH_DQ         (FLASH_DQ),
    .FLASH_WEn        (FLASH_WEn),
    .FLASH_OEn        (FLASH_OEn),
    .FLASH_CEn        (FLASH_CEn),
    
    .DDR_INIT_DONE    (ddr_init_done),
    
    .LCD_GPIO         (LCD_GPIO),
`endif
    .CLK              (clk),
    .LOCKED           (locked),
/*
    .M_UC_AWADDR      (uc_s_awaddr  ),
    .M_UC_AWVALID     (uc_s_awvalid ),
    .M_UC_AWREADY     (uc_s_awready ),
    .M_UC_WDATA       (uc_s_wdata   ),
    .M_UC_WSTRB       (uc_s_wstrb   ),
    .M_UC_WVALID      (uc_s_wvalid  ),
    .M_UC_WREADY      (uc_s_wready  ),
    .M_UC_BRESP       (uc_s_bresp   ),
    .M_UC_BVALID      (uc_s_bvalid  ),
    .M_UC_BREADY      (uc_s_bready  ),
    .M_UC_ARADDR      (uc_s_araddr  ),
    .M_UC_ARVALID     (uc_s_arvalid ),
    .M_UC_ARREADY     (uc_s_arready ),
    .M_UC_RDATA       (uc_s_rdata   ),
    .M_UC_RRESP       (uc_s_rresp   ),
    .M_UC_RVALID      (uc_s_rvalid  ),
    .M_UC_RREADY      (uc_s_rready  ),
*/
    .M_PAB_AWADDR      (pab_s_awaddr  ),
    .M_PAB_AWVALID     (pab_s_awvalid ),
    .M_PAB_AWREADY     (pab_s_awready ),
    .M_PAB_WDATA       (pab_s_wdata   ),
    .M_PAB_WSTRB       (pab_s_wstrb   ),
    .M_PAB_WVALID      (pab_s_wvalid  ),
    .M_PAB_WREADY      (pab_s_wready  ),
    .M_PAB_BRESP       (pab_s_bresp   ),
    .M_PAB_BVALID      (pab_s_bvalid  ),
    .M_PAB_BREADY      (pab_s_bready  ),
    .M_PAB_ARADDR      (pab_s_araddr  ),
    .M_PAB_ARVALID     (pab_s_arvalid ),
    .M_PAB_ARREADY     (pab_s_arready ),
    .M_PAB_RDATA       (pab_s_rdata   ),
    .M_PAB_RRESP       (pab_s_rresp   ),
    .M_PAB_RVALID      (pab_s_rvalid  ),
    .M_PAB_RREADY      (pab_s_rready  ),

    .M_AN_AWADDR      (an_s_awaddr  ),
    .M_AN_AWVALID     (an_s_awvalid ),
    .M_AN_AWREADY     (an_s_awready ),
    .M_AN_WDATA       (an_s_wdata   ),
    .M_AN_WSTRB       (an_s_wstrb   ),
    .M_AN_WVALID      (an_s_wvalid  ),
    .M_AN_WREADY      (an_s_wready  ),
    .M_AN_BRESP       (an_s_bresp   ),
    .M_AN_BVALID      (an_s_bvalid  ),
    .M_AN_BREADY      (an_s_bready  ),
    .M_AN_ARADDR      (an_s_araddr  ),
    .M_AN_ARVALID     (an_s_arvalid ),
    .M_AN_ARREADY     (an_s_arready ),
    .M_AN_RDATA       (an_s_rdata   ),
    .M_AN_RRESP       (an_s_rresp   ),
    .M_AN_RVALID      (an_s_rvalid  ),
    .M_AN_RREADY      (an_s_rready  ),

    .M_EX_AWADDR      (ex_s_awaddr  ),
    .M_EX_AWVALID     (ex_s_awvalid ),
    .M_EX_AWREADY     (ex_s_awready ),
    .M_EX_WDATA       (ex_s_wdata   ),
    .M_EX_WSTRB       (ex_s_wstrb   ),
    .M_EX_WVALID      (ex_s_wvalid  ),
    .M_EX_WREADY      (ex_s_wready  ),
    .M_EX_BRESP       (ex_s_bresp   ),
    .M_EX_BVALID      (ex_s_bvalid  ),
    .M_EX_BREADY      (ex_s_bready  ),
    .M_EX_ARADDR      (ex_s_araddr  ),
    .M_EX_ARVALID     (ex_s_arvalid ),
    .M_EX_ARREADY     (ex_s_arready ),
    .M_EX_RDATA       (ex_s_rdata   ),
    .M_EX_RRESP       (ex_s_rresp   ),
    .M_EX_RVALID      (ex_s_rvalid  ),
    .M_EX_RREADY      (ex_s_rready  ),

    .S0_PAB_AWADDR      (pab_m0_awaddr  ),
    .S0_PAB_AWVALID     (pab_m0_awvalid ),
    .S0_PAB_AWREADY     (pab_m0_awready ),
    .S0_PAB_WDATA       (pab_m0_wdata   ),
    .S0_PAB_WSTRB       (pab_m0_wstrb   ),
    .S0_PAB_WVALID      (pab_m0_wvalid  ),
    .S0_PAB_WREADY      (pab_m0_wready  ),
    .S0_PAB_BRESP       (pab_m0_bresp   ),
    .S0_PAB_BVALID      (pab_m0_bvalid  ),
    .S0_PAB_BREADY      (pab_m0_bready  ),
    .S0_PAB_ARADDR      (pab_m0_araddr  ),
    .S0_PAB_ARVALID     (pab_m0_arvalid ),
    .S0_PAB_ARREADY     (pab_m0_arready ),
    .S0_PAB_RDATA       (pab_m0_rdata   ),
    .S0_PAB_RRESP       (pab_m0_rresp   ),
    .S0_PAB_RVALID      (pab_m0_rvalid  ),
    .S0_PAB_RREADY      (pab_m0_rready  ),
    
    .M0_PAB_AWADDR      (pab_s0_awaddr  ),
    .M0_PAB_AWVALID     (pab_s0_awvalid ),
    .M0_PAB_AWREADY     (pab_s0_awready ),
    .M0_PAB_WDATA       (pab_s0_wdata   ),
    .M0_PAB_WSTRB       (pab_s0_wstrb   ),
    .M0_PAB_WVALID      (pab_s0_wvalid  ),
    .M0_PAB_WREADY      (pab_s0_wready  ),
    .M0_PAB_BRESP       (pab_s0_bresp   ),
    .M0_PAB_BVALID      (pab_s0_bvalid  ),
    .M0_PAB_BREADY      (pab_s0_bready  ),
    .M0_PAB_ARADDR      (pab_s0_araddr  ),
    .M0_PAB_ARVALID     (pab_s0_arvalid ),
    .M0_PAB_ARREADY     (pab_s0_arready ),
    .M0_PAB_RDATA       (pab_s0_rdata   ),
    .M0_PAB_RRESP       (pab_s0_rresp   ),
    .M0_PAB_RVALID      (pab_s0_rvalid  ),
    .M0_PAB_RREADY      (pab_s0_rready  ),
    
    .S_C0_AWADDR   (an_up_awaddr   ),
    .S_C0_AWLEN    (an_up_awlen    ),
    .S_C0_AWVALID  (an_up_awvalid  ),
    .S_C0_AWREADY  (an_up_awready  ),
    .S_C0_WDATA    (an_up_wdata    ),
    .S_C0_WSTRB    (an_up_wstrb    ),
    .S_C0_WLAST    (an_up_wlast    ),
    .S_C0_WVALID   (an_up_wvalid   ),
    .S_C0_WREADY   (an_up_wready   ),
    .S_C0_BRESP    (an_up_bresp    ),
    .S_C0_BVALID   (an_up_bvalid   ),
    .S_C0_BREADY   (an_up_bready   ),
    .S_C1_AWADDR   (an_dn_awaddr   ),
    .S_C1_AWLEN    (an_dn_awlen    ),
    .S_C1_AWVALID  (an_dn_awvalid  ),
    .S_C1_AWREADY  (an_dn_awready  ),
    .S_C1_WDATA    (an_dn_wdata    ),
    .S_C1_WSTRB    (an_dn_wstrb    ),
    .S_C1_WLAST    (an_dn_wlast    ),
    .S_C1_WVALID   (an_dn_wvalid   ),
    .S_C1_WREADY   (an_dn_wready   ),
    .S_C1_BRESP    (an_dn_bresp    ),
    .S_C1_BVALID   (an_dn_bvalid   ),
    .S_C1_BREADY   (an_dn_bready   ),

    .S_EX_ARID        (ex_m_arid      ),
    .S_EX_ARADDR      (ex_m_araddr    ),
    .S_EX_ARLEN       (ex_m_arlen     ),
    .S_EX_ARSIZE      (ex_m_arsize    ),
    .S_EX_ARBURST     (ex_m_arburst   ),
    .S_EX_ARVALID     (ex_m_arvalid   ),
    .S_EX_ARREADY     (ex_m_arready   ),
    .S_EX_RID         (ex_m_rid       ),
    .S_EX_RDATA       (ex_m_rdata     ),
    .S_EX_RRESP       (ex_m_rresp     ),
    .S_EX_RLAST       (ex_m_rlast     ),
    .S_EX_RVALID      (ex_m_rvalid    ),
    .S_EX_RREADY      (ex_m_rready    ),
    .S_EX_AWID        (ex_m_awid      ),
    .S_EX_AWADDR      (ex_m_awaddr    ),
    .S_EX_AWLEN       (ex_m_awlen     ),
    .S_EX_AWSIZE      (ex_m_awsize    ),
    .S_EX_AWBURST     (ex_m_awburst   ),
    .S_EX_AWVALID     (ex_m_awvalid   ),
    .S_EX_AWREADY     (ex_m_awready   ),
    .S_EX_WDATA       (ex_m_wdata     ),
    .S_EX_WSTRB       (ex_m_wstrb     ),
    .S_EX_WLAST       (ex_m_wlast     ),
    .S_EX_WVALID      (ex_m_wvalid    ),
    .S_EX_WREADY      (ex_m_wready    ),
    .S_EX_BID         (ex_m_bid       ),
    .S_EX_BRESP       (ex_m_bresp     ),
    .S_EX_BVALID      (ex_m_bvalid    ),
    .S_EX_BREADY      (ex_m_bready    )
  );
    
  assign LED = DIP;
  assign LED_E = ddr_init_done;
  assign LED_C = locked;
  assign LED_W = linkup;
  assign LED_N = 1'b0;
  assign LED_S = 1'b0;
endmodule
